This invention relates to programmable logic devices (“PLDs”), and more particularly to clock circuitry for use on PLDs. An important purpose of this clock circuitry is to help the PLD support various high-speed serial data signaling schemes or protocols.
PLDs are intended as relatively general-purpose devices. A PLD can be made more useful by increasing the number of functions it can perform. In the area of data communication, there is increasing interest in high-speed serial data communication. This communication may take any of a large number of forms. For example, such communication may be via one channel or via several channels that can operate relatively independently of one another. Alternatively or in addition, such communication may be via several channels that must be highly synchronized with one another. The number of channels employed may vary considerably. For example, four synchronized channels may be needed, or eight synchronized channels may be needed. Very high serial data rates may be needed (e.g., anywhere from 622 Mbps (megabits per second) to 6.5 Gbps (gigabits per second)). Elsewhere on the PLD that data is typically handled in parallel form, which may have any of several different formats (e.g., 8-bit bytes, 10-bit bytes, two parallel 8-bit bytes, or two parallel 10-bit bytes), and the transmitter circuitry needs to be able to serialize data having any of those parallel formats.
The proliferation of serial data communication protocols that it would be desirable for a PLD to be able to support calls for continued improvement of PLD serial data transmitter circuitry. This is particularly true with regard to the clock circuitry that is provided on a PLD to support various serial data transmission options. Channels that are operating independently or relatively independently of one another may need independent or relatively independent clock signals, and those signals may need to have a number of different frequencies and/or other different characteristics. On the other hand, communication protocols that require a large number of synchronized channels (e.g., up to eight channels) need the support of clock signals that can be generated in a highly centralized manner and then efficiently distributed to all of the channels that will use those clock signals.